The invention relates to a data memory for storing data, in which the supply voltage lines are additionally buffered by the storage capacities of redundant memory cells.
FIG. 1 shows, schematically, a data memory for storing in accordance with the prior art. The data memory has a memory cell array having a large number of memory cells. In this case, each memory cell comprises a select transistor and a storage capacity for storing one data bit. The memory cells are addressed via the select transistors, which are connected via word lines and bit lines to address decoders. The memory cell array contains redundant memory cells SZRED, which are provided in order to replace memory cells which have been produced wrongly in the production process The redundant memory cells are driven by the address decoders via associated word lines WLRED and bit lines BLRED. The address decoders are connected to fuse-blocks, as they are known, or readdressing lines, which map or readdress the addresses of memory cells that have been produced wrongly to addresses of redundant memory cells. The memory cell array produced is subjected to a testing operation following the production process and the fuse-blocks are programmed in such a way that the addresses of the memory cells produced wrongly are remapped to the redundant memory cells SZRED. The fuse-blocks or readdressing circuits contain fuses or fuse links such as laser fuses or electric fuses. The fuses comprise metal strips, for example, which are severed for the purpose of readdressing. To this end, the fuse-blocks are programmed via programming lines P. The fuse-blocks or readdressing circuits are connected to the internal address bus of the data memory. The memory cell array contains read amplifiers to read the data bits stored in the memory cells. Here, the read amplifiers comprise operational amplifiers, which amplify the voltage difference between a bit line and a reference potential and output it at a data output. The data D read out is output via a data bus for further processing. The read amplifiers within the memory cell array are connected, via internal voltage supply lines within the memory cell array, to a supply voltage terminal, which is connected via an external supply voltage line to the output of a supply voltage source VQ. The externally applied supply voltage is buffered by a buffer capacitor with a high capacitance in order to balance out the voltage fluctuations.
One disadvantage of the data memory according to the prior art, illustrated in FIG. 1, is that the external supply voltage line between the output of the external supply voltage source VQ and the supply voltage terminal VSS of the memory cell array is relatively long. Because of the relatively high line length, the resistance R of the external supply voltage line is relatively high. Because of the high storage capacity of the supply voltage buffer capacitor CP, the time constant xcfx84 which results from the product of the line resistance R of the external supply voltage line and the capacitance of the buffer capacitor CP is high. The buffering of the supply voltage for these amplifiers within the memory cell array is therefore relatively sluggish, so that the electric charge needed for the loads contained in the memory cell array cannot be supplied quickly enough by the buffered supply voltage. Because of the sluggishness of the buffered supply voltage, voltage peaks or local brief voltage dips on the supply voltage lines for the read amplifiers cannot be compensated for quickly enough, so that it is possible for read errors to occur when reading the stored data bits.
It is therefore the object of the present invention to provide a data memory for storing data whose supply voltage is buffered with a low sluggishness.
According to the invention, this object is achieved by the data memory having the features specified in patent claim 1.
The invention provides a data memory for storing data having
a memory cell array, which comprises a large number of memory cells, each of which can be addressed by means of a memory cell select transistor connected to a word line and to a bit line and which have a storage capacity for storing one data bit,
the memory cell array containing redundant memory cells, which are provided in order to replace memory cells which have been produced wrongly, by means of readdressing, and having
read amplifiers, which are in each case provided for the signal amplification of a data bit read from an addressed memory cell via an associated bit line and are supplied with a buffered supply voltage,
the excess redundant memory cells which have not been readdressed being connected to the associated bit lines and additionally buffering the supply voltage for the read amplifiers.
In the case of the data memory according to the invention, the capacities of the excess redundant memory cells which are not needed to repair the memory cells that have been produced wrongly are used for the additional buffering of the supply voltage lines for the read amplifiers. The word lines of the data memory according to the invention are preferably connected to a word line decoder, and the bit lines are preferably connected to an associated bit line decoder.
In a preferred embodiment of the data memory according to the invention, the word line decoder and the bit line decoder are in each case connected to a readdressing circuit, which remap the addresses of memory cells that have been produced wrongly to the addresses of redundant memory cells within the memory cell array.
The word lines of the excess redundant memory cells that have not been readdressed are connected to a voltage potential in order to turn on the associated select transistors of the memory cells.
The bit lines of the excess redundant memory cells that have not been readdressed are preferably connected to the buffered supply voltage.
Each memory cell of the memory cell array preferably has a storage capacitor with a storage capacity for storing one data bit.
The supply voltage for the read amplifiers is preferably generated by an external voltage supply source and output at an output of the supply voltage source, a buffer capacitor with a high capacitance being connected between the output of the supply voltage source and a reference potential in order to buffer the supply voltage.
In a particularly preferred embodiment of the data memory according to the invention, the bit lines of the redundant memory cells are connected to gate terminals of field effect transistors, which are connected to internal supply voltage lines for the read amplifiers of the non-redundant memory cells.
The supply voltage buffered by the buffer capacitor is preferably connected via an external supply voltage line to the read amplifiers in order to supply them with voltage.
In this case, the line lengths of the bit lines between the memory cells and the read amplifiers are preferably significantly shorter than the line length of the external supply voltage line.
In a particularly preferred embodiment of the data memory according to the invention, the redundant memory cells within the memory cell array are arranged close to the read amplifiers.
The data memory is preferably a DRAM memory.
In the further text, a preferred embodiment of the data memory according to the invention will be described in order to explain features essential to the invention.